Background Art
In a reference amplifier (as shown in FIG. 9) of a semiconductor memory device disclosed in Japanese Unexamined Published Patent Application No. 2001-312895 (“Patent Document 1”), during serial access operations, an L-level control signal (RCL) is provided to the input terminal of an inverter 206 so that a Pch-type MOS transistor 203 enters a shut-off state and the reference amplifier operates as a ratio circuit in accordance with the functioning of a Pch-type MOS transistor 201 and an Nch-type MOS transistor 204.
During latency, an H-level control signal (RCL) is input to the input terminal of the inverter 206 so that the Pch-type MOS transistor 203 enters a conductive state (i.e., becomes conductive), and the reference amplifier operates as a ratio circuit in accordance with the functioning of Pch-type MOS transistors 201 to 203 and the Nch-type MOS transistor 204.
Thus, a reference signal (REF) is at a high level during latency and is at a low level during the serial access operation. Since the level of the reference signal is high during the latency, a comparison between a sense level that drops as a word line rises and the level of a reference signal is performed at an early stage. In addition, since the level of the reference signal is low during the serial access operation, a comparison between a sense level that increases during precharging and the level of the reference signal is also performed at an early stage. In this way, the speed of data detection is increased.
Problem the Invention Solves
Patent Document 1 is associated with a technique for selecting the level of a reference signal during each of a latency phase and a serial access phase to accelerate the comparison made during data detection in each phase.
However, during a period from the start of reading out a reference signal from a dummy cell (reference cell) until the level of the reference signal reaches a predetermined value, a specified period of time elapses due to the propagation time constant of a signal caused by a load in a reference data readout path such as a bit line. Also, during while precharging a data readout path and the reference data readout path prior to readout of data, a specified period of time elapses before a predetermined precharge level is reached due to the propagation time constants of signals caused by loads in these paths. These propagation time constants are believed to fluctuate or vary, owing to various fluctuation factors such as diverse operating conditions and production variations.
Data detection by a sense amplifier circuit should be performed after readout data and readout reference data have reached a satisfactory level. To reliably read out data in spite of fluctuations in the propagation time constants, the detection of the data has to be performed after sufficient time has elapsed from readout of the data and reference data started, taking into account fluctuation and variation factors. This may act as a disincentive to high-speed readout access operations and is therefore disadvantageous.